Readings
Description
This assignment will focus on creating digital circuits. The main tasks are:
- building and testing NWay plexers
- building and testing circuits for addition
Build the circuits described in Project 2 (except
ALU, but including
Mux4Way, Mux8Way, DMux4Way, DMux8Way from Project 1):
N2T: Project 2
Chapter 2 provides the contract for each circuit, i.e. description of its behavior, names and number inputs, names and state of outputs. The API is available here:
The Hack Chipset
What to Submit
Inside folder
computer create folder
arithmetic (with the required subfolders listed below). Zip folder
arithmetic in file named
arithmetic.zip and upload it to the Moodle dropbox. When
arithmetic.zip is unzipped it should produce folder
arithmetic with the required subfolders and files inside.
HDL/Logisim Notes
Click the thumbnail for notes on
Splitter and
Constant in HDL and Logisim:
Design in Logisim
Note the following requirements:
- arrange the circuits vertically in the given order (each below the previous one, *not* in a grid)
- label the input pins as specified in the contract (ok that there will be duplicate names)
Here are additional specific requirements:
- save the Logisim files in folder
computer/arithmetic/circ
- see notes above on
Constant and Splitter
Mux4Way16, Mux8Way16:
- save in files named Mux4Way16.circ and Mux8Way16.circ
- basic gates should be avoided if possible
Mux4Way16 should be built primarily of Mux16; as few as possible
Mux8Way16 should be built primarily of Mux16,Mux4Way16; as few as possible
- Logisim has a single Multiplexer component whose properties can be changed to have the desired number of inputs and bus widths
DMux4Way, DMux8Way:
- save in files named DMux4Way.circ and DMux8Way.circ
- basic gates should be avoided if possible
DMux4Way should be built primarily of DMux; as few as possible
DMux8Way should be built primarily of DMux,DMux4Way; as few as possible
- Logisim has a single Demultiplexer component whose properties can be changed to have the desired number of outputs and bus widths
HalfAdder, FullAdder:
- save in file named HalfFullAdder.circ
- do not use within each other
- only basic gates may be used; as few as possible
Add16:
- save in file named Add16.circ
- despite the name, for the Logisim version the two inputs will be of width 6, i.e. the Adder will only add 6 bit numbers
- the circuit should be built of
Adder components (under Arithmetic) whose pins have width 1; these will represent Half/FullAdder depending on how they are used
- basic gates should be avoided, if possible
Inc16:
- save in file named Inc16.circ
- despite the name, for the Logisim version the inputs will be of width 6, i.e. the circuit will only increment 6 bit numbers
- build with suitably sized
Adder
- basic gates should be avoided, if possible
Design in HDL
Here are additional specific requirements:
- implement one circuit at a time; for circuit X copy only X.cmp, X.tst to folder computer/arithmetic/hdl
- for each circuit click button Add File to add X.hdl (a blank file); see class examples for syntax
- see notes above on
Constant and Splitter
Mux4Way16, Mux8Way16:
- basic gates should be avoided, if possible
Mux4Way16 should be built primarily of Mux16; as few as possible
Mux8Way16 should be built primarily of Mux16,Mux4Way16; as few as possible
DMux4Way, DMux8Way:
- basic gates should be avoided, if possible
DMux4Way should be built primarily of DMux; as few as possible
DMux8Way should be built primarily of DMux,DMux4Way; as few as possible
HalfAdder, FullAdder:
- do not use within each other
- only basic gates may be used; as few as possible
Add16:
- built primarily out of
HalfAdder,FullAdder
- basic gates should be avoided, if possible
Inc16:
- ok to use any of the previous chips
- basic gates should be avoided, if possible
The End