HDL/Logisim Notes

Logisim Notes

• Splitter: to merge/split wires:
  • use component Splitter under Wiring
  • the merge/split depends on the point of view (i.e. on the orientation)
  • orientation can be set via the Properties panel

• Constants: to achieve the effect of sending a constant value:
  • use component 1⚬Constant under Wiring
  • the default value is 1 of bit width 1 (can change via the Properties)
  • it can also send 0, but by default Logisim sets pins to 0, so constant 0 is rarely needed

HDL Notes

• Splitter: to achieve the effect of splitting wires in HDL you write:

  for the case when left,right are in/out pins: widths have to match left,right cannot be mixed type, i.e. one in, other out is not allowed
  range version	1-bit version
  left[i..j]=right	left[i]=right
  left=right[p..q]	left=right[p]
  left[i..j]=right[p..q]	left[i]=right[p]

  for the case when right is local wire: the first creates a local wire of the given width the second uses already created wire local wire cannot have [], it inherits assigned width, but can create several local wires as in last step
  range version	1-bit version
  outPin[i..j]=wire	outPin[i]=wire	← creates local wire
  inPin[i..j]=wire	inPin[i]=wire	← attaches created wire
  ...,outPin[i0..j0]=wire0,     outPin[i1..j1]=wire1,     outPin[i2]=wire2,...		← creates several local wires      from same output pin

• Constants: to achieve the effect of sending the constant values 1 or 0 to a pin in HDL you write:

  inPin[i..j]=true	inPin[i..j]=false
  inPin[i]=true	inPin[i]=false
  inPin=true	inPin=false	← assign all bit lines