CS 221
Computer Organization and Assembly Language Programming

Fall 2026

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Software

See Quiz 4. For CS Lab computers in Terminal type:

• logisim to run Logisim
• hwsim to run Hardware Simulator

Readings

• Gates:
  • N2T: Chapter 1 (skip p. 25) (slides 3-4, 21-end)

• HDL class examples:
  • Invite.hdl | Invite.cmp | Invite.tst
  • Invite16.hdl | Invite16.cmp | Invite16.tst
  • Invite-messy.hdl a version of Invite.hdl with poor choice of pin names for this example

• HDL book examples (page 16):
  • Xor.hdl | Xor.cmp | Xor.tst
  • Xor16.hdl | Xor16.cmp | Xor16.tst

Description

This assignment will focus on creating digital circuits. The main tasks are:

• building and testing digital circuits in Logisim
• describing digital circuits in Hardware Description Language and testing the description in the Hardware Simulator

Build the circuits described in Project 1 (except Mux4Way16, Mux8Way16, DMux4Way, DMux8Way):

N2T: Project 1

Chapter 1 provides the contract for each circuit, i.e. description of its behavior, names and number inputs, names and state of outputs. The API is available here:

The Hack Chipset

What to Submit

Folder computer has already been created in the DrJava folder.

Inside folder computer create folder basic (with the required subfolders listed below). Zip folder basic in file named basic.zip and upload it to the Moodle dropbox. When basic.zip is unzipped it should produce folder basic with the required subfolders and files inside.

HDL/Logisim Notes

Click the thumbnail for notes on Splitter and Constant in HDL and Logisim:

Design in Logisim

Note the following additional requirements:

• arrange the circuits vertically in the given order (each below the previous one, *not* in a grid)
• label the input pins as specified in the contract (ok that there will be duplicate names)

Here are a few comments on Logisim:

• Splitter: Logisim has a component called Splitter under Wiring; it can be used to split or merge wires depending on the point of view (i.e. on the orientation); it can be oriented appropriately via the Properties panel

Here are additional specific requirements:

• save the Logisim files in folder computer/basic/circ
• label the input pins as specified in the contract
• see notes above on Splitter

• Not, And, Or, Xor:
  • save in file named Basic.circ
  • only Nand, Not gates may be used; for Not only Nand

• Not16, And16, Or16, Xor16:
  • save in file named Basic16.circ
  • only Nand16, Not16 gates may be used; for Not16 only Nand16

• Or8Way:
  • save in file named Or8Way.circ
  • note that in the contract the input is 1 pin of width 8, so split immediately into 8 wires of width 1 (use Splitter under Wiring)
  • only Basic gates with 2 input pins of width 1 allowed
  • minimize circuit depth, i.e. #levels to right; (hint: merge sort)

• Mux/Mux16:
  • save in file named Mux.circ
  • only Basic/Basic16 gates allowed
  • for the select input use Bit Extender

• DMux/DMux16:
  • save in file named DMux.circ
  • only Basic/Basic16 gates allowed
  • the select input will need to be widened (use Bit Extender under Wiring)

• Mux4Way16, Mux8Way16, DMux4Way, DMux8Way:
  • ignore

Design in HDL

Use our class editor to create and test the required .hdl files given by the authors. Note the following additional requirements:

• implement one circuit at a time; for circuit X copy only X.cmp, X.tst to folder computer/basic/hdl

• for each circuit click button Add File to add X.hdl (a blank file); see class examples for syntax

• see notes above on Splitter

• Not, And, Or, Xor:
  • only Nand, Not gates may be used; for Not only Nand

• Not16, And16, Or16, Xor16:
  • only Nand16, Not16 gates may be used; for Not16 only Nand16
  • Nand16 is not built-in, so create your own Nand16.hdl, Nand16.cmp, Nand16.tst (for the last two model after And16 versions)
  • for Xor16 reimplement Xor16.hdl and use its test files

• Or8Way:
  • only Basic gates with 2 input pins of width 1 allowed
  • minimize circuit depth, i.e. #levels to right; (hint: merge sort)

• Mux, DMux:
  • only Basic gates allowed

• Mux16, DMux16:
  • only Basic16 gates allowed and Extender16
  • Extender16:
    • needed for Mux16 and DMux16
    • download the following file and complete the code for the chip:

      Extender16.hdl (also create your own Extender.tst, Extender.cmp)

  • create your own DMux16.hdl, DMux16.tst, DMux16.cmp; model after Mux16
  • from main menu: View→View→Output (shows output of your circuit); View→View→Compare (shows expected result);

• Mux4Way16, Mux8Way16, DMux4Way, DMux8Way:
  • ignore

The End