Readings
- ALU:
- N2T: Section 2.2.2, 2.3 (p39), 2.4, 2.5 (slides 44-58, 65)
Description
This assignment will focus on the following tasks:
- building the major computing device, the ALU
- building simple memory components
Build the
ALU circuit described in Project 2:
N2T: Project 2
Chapter 2 provides the contract for each circuit, i.e. description of its behavior, names and number inputs, names and state of outputs. The API is available here:
The Hack Chipset
Design in Logisim
Note the following requirements:
- arrange the circuits vertically in the given order (each below the previous one, *not* in a grid)
- label the input pins as specified in the contract
Here are additional specific requirements:
- save the Logisim files in folder
computer/alu/circ
ALU:
- save in file named ALU.circ
- recall that Multiplexers have "if" meaning
- use the Logisim versions of previously built-components (e.g.
Adder)
- you may convert a single
Or component into Or16Way
- minimal use of basic gates
- note on testing:
- initially do not include the (status) outputs
zr, and ng
- after the
ALU can perform the operations in Table 2.6, add the (status) outputs
- submit screenshots that show evidence of testing based on the following configurations in Table 2.6:
- save in folder
computer/alu/png
- each image size no larger than 250KB, just take a screenshot of the circuit
- row1.png: control pins set as in row for
0 with inputs x=0..01011,y=0..01001
- row2.png: control pins set as in row for
1 with inputs x=0..01011,y=0..01001
- row3.png: control pins set as in row for
-1 with inputs x=0..01011,y=0..01001
- row5.png: control pins set as in row for
y with inputs x=0..01011,y=0..01001
- row6.png: control pins set as in row for
!x with inputs x=0..01011,y=0..01001
- row9.png: control pins set as in row for
-y with inputs x=0..01011,y=0..01001
- row10.png: control pins set as in row for
x+1 with inputs x=0..01011,y=0..01001
- row13.png: control pins set as in row for
y-1 with inputs x=0..01011,y=0..01001
- row16.png: control pins set as in row for
y-x with inputs x=0..01011,y=0..01001
- row18.png: control pins set as in row for
x|y with inputs x=0..01011,y=0..01001
- in a textbox in image row18.png list the test cases that failed, or
write Works Correctly
Design in HDL
Here are additional specific requirements:
- Implement one circuit at a time. For circuit X copy X.hdl, X.cmp, X.tst to folder computer/alu/hdl.
Or16Way:
- create
Or16Way chip saved in Or16Way.hdl; as simple as possible with as few gates as possible; reuse similar existing chips from previous assignments
- create your own Or16Way.hdl, Or16Way.tst, Or16Way.cmp; model after the existing similar version (it is fine to just copy each data value twice to match the width)
ALU:
- recall that Multiplexers have
"if" meaning
- use the chips built in previous assignments (e.g. Adder); do not copy your code, so that it uses the book versions
- minimal use of basic gates
- note on testing:
- initially ignore the (status) outputs
zr,ng; simply do not mention them anywhere in ALU.hdl
- for testing use the provided files ALU-basic.tst and ALU-basic.cmp (no status)
- later add the (status) outputs
zr,ng and for testing use the provided files ALU.tst and ALU.cmp (with status)
